1. Field of the Invention
The present invention generally relates to integrated circuit fabrication processes and, in particular, to a method for improving step coverage in very large scale integration (VLSI) semiconductor die fabrication.
2. Description of the Related Art
VLSI technology research and development in integrated circuit fabrication has resulted in semiconductor chips in which the geometry of individual components is continuously scaled down in order to improve performance and to conserve chip area for better manufacturing yield. One of the inherent problems in the microscopic dimensioning of the die is that interconnection of the individual components requires the filling of one or more contact apertures per component in layers formed over each individual active component. These apertures, also known as "contact windows" and "vias," typically lead down through the insulator to the contact area of each active device which is to be electrically coupled. That is to say, although to the naked eye a semiconductor die appears to be flat, it is, in fact, a nonplanar environment.
Currently, down-scaling is carried out horizontally; the vertical dimension is not scaled proportionally. This causes a very severe problem in fabrication processes, commonly referred to as "step coverage." In VLSI, the horizontal dimension for component surface areas is currently approaching the 1 micron range, with submicron dimensioning being considered as the breakthrough target. However, the vertical height, or depth, of vias may not be amenable to this scaling due to detrimental phenomena such as parasitic capacitance effects.
The standard electrical interconnection mechanism in the current state of the art is basically a patterned thin film of metal. The process procedures for forming the interconnections is commonly referred to as "metallization." In particular, a commonly used method of metallization is to sputter a metal layer onto an insulating layer, such as silicon dioxide ("oxide") which has been deposited on the whole chip area and has etched vias leading down to the substrate diffusion regions, polysilicon lines, and underlying metal lines for the completion of the desired interconnection between various components.
As depicted in FIG. 1, the relatively deep contact apertures in a VLSI die are not suited to sputtered metal films which provide adequate step coverage. The result is the occurrence of poor step coverage. Poor step coverage results in both poor reliability and many inoperative devices being formed on a wafer, i.e., low manufacturing yield.
If the metallization is an interstructural layer, the step coverage problem becomes compounded in subsequently deposited layers, unless planarization is performed on the metal layer.
One method of overcoming poor step coverage is to attempt to planarize the metallization layer after it has been formed. This method is a relatively high temperature process. High temperatures can have detrimental effects upon the semiconductor layers in which the active components have been formed. One such effect is the lateral and vertical spreading of doped regions. In a bipolar transistor, for example, an extrinsic base region may spread through an intrinsic base region and into the emitter region, or junction depths may spread down toward a buried collector region, resulting in lower breakdown voltages. In both metal-oxidesemiconductor (MOS) and bipolar devices, migration of impurities can occur during the heating cycle.
Another method is to create a relatively high phosphorus (P) concentration in the oxide layer and use high temperature after the contact etch to smooth the corners of the contact holes. Again, a disadvantage is the undesirable high temperature cycle after the formation of the source/drain of MOS transistors. The overall structure retains relatively poor surface contours for subsequent metallization processes. To overcome the high temperature requirement for P-doped oxide, the oxide can be doped with both boron (B) and phosphorus (P). However, this introduces a difficulty of the process control of the compositions of the oxide film.
Yet another method is to employ an etch technique which will result in tapered vias. This method, however, requires very delicate masking operations. Reproducibility in such a technique is difficult to achieve.
A further method has been developed to improve the step coverage by employing a gas phase reaction at low pressure, i.e., a low pressure chemical vapor deposition (LPCVD) process. However, LPCVD metal suffers from high resistivity and lack of film thickness uniformity.
Another method of improving step coverage is a doped, polysilicon plug and etch-back planarization technique taught in U.S. patent application No. 761,206 (Sander), filed July 31, 1985, and assigned to the common assignee of the present application.
In general, poor step coverage forces the semiconductor chip manufacturer to use techniques which are contrary to VLSI. Examples include: the formation of vias with inwardly sloping sidewalls, viz., retaining relatively wide window mouths; constraining spacing reduction so that high accuracy alignment of the bias is ensured, such as for complementary MOS (CMOS) devices where a p-type region may be located in an n-type well and the contact must be made only to the p-type region.
A related problem, "spiking," can occur in VLSI devices because of shallow junction depths of doped regions in the semiconductor substrate. When contacted directly by metal, such as aluminum, atoms of the metal can migrate down through the junction into a lower layer of the component structure. This also results in losses in yield and reliability.
Hence, there is a need for an integrated circuit fabrication technique for improving step coverage having better scalability while providing good ohmic contacts.